Optical phased array structure and fabrication techniques

ABSTRACT

Methods of manufacturing and using a monolithically integrated optical phase array (OPA) chip device, and the device itself. A three-dimensional (3-D) integrated optical phase array (OPA) chip device. A method of manufacturing a two-dimensional sparse optical phase array by layout-constrained array factor optimization. A system of complementary metal-oxide-semiconductor (CMOS) electronics integrated with a three-dimensional integrated optical array chip device. A method of three-dimension vertical coupling to improve optical power in optical phase arrays.

RELATED APPLICATIONS

This applications claims priority to U.S. provisional application No.62/910,933, filed on Oct. 4, 2019, the contents of which areincorporated by reference in their entirety.

This invention was made with government support under IIS1722847 awardedby National Science Foundation. The government has certain rights in theinvention.

FIELD

This application is related to the field of silicon photonics andoptical phase array design.

BACKGROUND

Integrated optical phased arrays (OPAs) are rapidly becoming one of themost promising technologies for light detection and ranging (LIDAR)applications. This is in part due to their advantages in cost, size,weight, reliability, and power consumption as compared to conventionalsolutions. Large-scale OPAs can leverage high integration densities ofelectronic-photonic integrated circuit (EPIC) technology to generatefiner beamwidth, and better beamsteering control.

To meet the stringent performance requirements in real worldapplications, OPAs need high output optical power, a large number ofemitters with smaller pitch size, and a large aperture. New arrayarchitectures, aperture physical designs, and emitter geometries arebeing developed to relax the tradeoffs in OPA designs. Fundamentally,these limitations not only come from basic phased array characteristics,but also from the underlying integrated photonics technology's physicalconstraints.

Currently, silicon photonics technologies are the dominant technologychoice for integrated OPA development. This is because of the lowfabrication cost and electronic-photonic integration capabilitiesenabled by mature silicon based semiconductor infrastructures driven byCMOS electronics industry. Silicon offers low-loss optical waveguidedevices for two main components of an OPA: the grating emitters and thephase shifters.

Silicon, however, may present some challenges in high-power, large-scaleOPA implementations. First, silicon waveguides may have relatively lowoptical power handling capability due to the large loss at high opticalpower caused by two-photon absorption. Secondly, silicon photonicdevices may be built on the top silicon layer of a silicon-on-insulator(SOI) chip. A single device layer may prohibit complex waveguide routingand severely limit how the array of emitters are connected to the phaseshifters, especially for two-dimensional (2-D) OPAs. Extra routing spaceis needed inside the emitter array, which reduces the OPA's fill factor.Lastly, the SOI layer structure also limits the emission efficiency ofthe grating emitter since light can propagate both up off the chip ordown into the substrate from the grating.

Further, 2-D OPAs continue scaling up to meet the performancerequirements for real world applications. New array architectures,aperture optimization methodologies, and novel array geometries areneeded to address fundamental tradeoffs for OPA's beamwidth andbeamsteering performance. On one hand, the footprint of the emitterneeds to be sufficiently large for reasonable emission efficiency. Onthe other hand, emitter pitch needs to be minimized so as to maximizethe sidelobe spacing and hence beamsteering range. Therefore, the ratiobetween the emitter footprint and emitter pitch, also referred to as thefill factor, becomes an important design metric, similar to that in animage sensor.

Conventional phased array designs rely heavily on rectangular gridgeometries due to their RF origin. Rectangular grids are desirablebecause mature analytic formulations for phased array analysis arereadily available from the RF domain and can be scaled to opticalfrequencies. System-level array design and analysis is streamlinedwithout the computational cost of directly modeling the full OPA on thedevice level. As the number of elements in the emitter array, andparticularly the number of emitters, scales up, however, the rectangulargrid design imposes some significant constraints on OPA performance.Because convention designs abstract the emitters as points on therectangular grid, routing waveguides to the emitters is not often takeninto account and left as an afterthought during the physicalimplementation (layout) of the array aperture. For one-dimensional (1-D)or small-scale 2-D arrays with fine emitter pitch, it is alreadydifficult to route the waveguides due to the crosstalk between adjacentwaveguides. For large-scale 2-D arrays, routing waveguides to emitterslocated at the array interior may become challenging.

SiN is an alternative material choice for silicon photonics. SiNwaveguides may have lower loss and higher optical power handlingcapability than their silicon counterparts. Multiple SiN layers may befabricated on a regular silicon substrate instead of the more expensiveSOI one. Hence SiN photonic devices may be more fully compatible withstandard CMOS technologies and may be integrated on the same chip withCMOS electronics. On the other hand, the thickness of a SiN thin filmmay be limited by mechanical stress to typically less than 200 nm. SinceSiN may have much smaller refractive index than silicon (about 1.5 vs3.4 at 1550 nm), optical confinement in SiN waveguides may be relativelypoor. Hence, SiN may not be suitable for compact grating emitters, andalso inefficient to implement thermal-optic phase shifters.

Moreover, many OPA based systems currently operate in one of threemodes: pulsed, amplitude modulated continuous wave (AMCW), or frequencymodulated continuous wave (FMCW). In the pulsed mode, the timinginformation is encoded and then decoded to and/or from its signal bypulses in the time domain, which is then translated into the targetdistance by the detection circuit in the receiver. In the AMCW or FMCWmode, the timing information is encoded and then decoded by a frequencysweep in either the RF modulation signal or the optical carrier signal.During each detection process, the OPA's optical beam is assumed to bedirected at a given angular position with static coefficients at theOPA's phase shifters. To scan the target scene by beamsteering, theOPA's phase shifter coefficients need to be changed multiple times. Ateach new setting, the detection can begin when the phase shiftercoefficients become stable after the transition. If thermo-optic phaseshifters are employed, this transition can take some time to completedue the slow heat diffusion across the whole phase shifter array. Thismay be impractical for applications that require fast performance. Suchslow transition not only slows down the beamsteering process, but alsoleads to larger power consumption since the heat dissipated to theenvironment during the transition is wasted.

There is a need for improved silicon photonic chips and optical phasearray design. This application addresses that need.

SUMMARY

An aspect of the application is a three-dimensional (3-D) integratedoptical phase array (OPA) device, comprising: an interposer, wherein theinterposer comprising photonic waveguide layers are on top of a siliconsubstrate and having at least one optical input/output port; an opticalpower distribution network, wherein the optical power distributionnetwork is located on the photonic waveguide layer of the interposer;and one or more OPA chiplets, wherein each OPA chiplet comprise phaseshifters and photonic waveguides and having at least one opticalinput/output port; wherein the at least one optical input/output portsof the OPA chiplets are coupled to the at least one of the opticalinput/output ports of the interposer; wherein the one or more OPAchiplets comprise emitter arrays (EA), and wherein the OPA chiplet canoperate in either transmit, receive, simplex, or duplex mode, whereinsimplex mode means that the OPA chiplet can transmit or receive atdifferent times, and duplex mode means that the OPA chiplet transmitsand receives at the same time.

In certain embodiments, the device wherein OPA chiplets are 3-Dintegrated on an interposer with at least one photonic waveguide layer,wherein the photonic waveguide layer is separated from the siliconsubstrate layer or another photonic waveguide layer by at least onecladding material. In certain embodiments, the device wherein at leastone photonic waveguide layer is fabricated on the silicon substrate andthen patterned using lithography to become part of the interposer. Incertain embodiments, the device wherein wherein one or more waveguideson the one or more OPA chiplets feeds one or more sub-arrays ofemitters, wherein each waveguide may feed a single emitter or a subarrayof emitters. In certain embodiments, the device wherein the one or moreOPA chiplets are integrated with the interposer by flip-chip bonding ormulti-chip module technologies or other 3-D integration technologies. Incertain embodiments, the device wherein a plurality of OPA chiplet arearranged in a column, and further wherein the OPA chiplets can bearranged in a 2-D array, wherein the 2-D array can comprise geometriesincluding square, rectangle, circle, triangle, diamond, hexagonal,octagonal, or other shapes. In certain embodiments, the device whereinthe EAs from all OPA chiplets form an overall OPA aperture for thedevice. In certain embodiments, the device wherein the opticaldistribution network comprises one or more selected from the group ofwaveguides, couplers, and passive devices to split an optical input froma laser source. In certain embodiments, the device wherein furthercomprising optical couplings that connects the interposer's opticalinput/output ports to the optical input/output ports on the one or moreOPA chiplets. In certain embodiments, the device wherein the coupling isbetween one or more input/output ports on the interposer and one or moreinput/output ports on the OPA chiplets. In certain embodiments, thedevice wherein the coupling is structured as horizontal throughedge-to-edge coupling. In certain embodiments, the device wherein thecoupling is structured as vertical by mode conversion between aplurality of waveguides. In certain embodiments, the device whereinfurther comprising an emission window. In certain embodiments, thedevice wherein the emission window is opened within the interposer asone or more through-substrate openings in the region aligned with the EAon the one or more OPA chiplets. In certain embodiments, the devicewherein the emission window is an opening at the backside of each OPAchiplets, wherein the opening can be patterned using etching or otherfabrication techniques. In certain embodiments, the device whereinfurther comprising a reflector, wherein the reflector is a mirror madeof a metal layer, or a grating, or other type of reflector, wherein thereflector may be on the interposer or on the OPA chiplet.

In certain embodiments, the OPA chiplet is built based on at least oneof the following photonics technologies: silicon photonics (SiPh),silicon nitride photonics (SiN), hybrid silicon photonics (SiPh withSiN), lithium niobate photonics (LN), or III-V photonics. In certainembodiments, the photonic waveguide layer comprises at least one ofsilicon, silicon nitride, lithium niobate, or III-V materials. Incertain embodiments, the OPA device is configured for multi-wavelengthoperation. In certain embodiments, the OPA device is configured formulti-beam operation.

Another aspect of the application is a method of building athree-dimensional integrated optical array chip device, comprising thesteps of: building an optical power distribution network on at least onephotonic waveguide layer; connecting one or more phase shifters to theoptical power distribution network; coupling one or more OPA chiplets tothe interposer; integrating the interposer with the one or more OPAchiplets; and wherein the one or more OPA chiplets comprise emitterarrays (EA) and phase shifters.

In certain embodiments, the method wherein the one or more OPA chipletsare integrated on top of the interposer. In certain embodiments, themethod wherein at least one photonic waveguide layer is fabricated ontop of the one or more OPA chiplets. In certain embodiments, the methodwherein one or more waveguides on the one or more OPA chiplets feeds oneor more sub-arrays of emitters. In certain embodiments, the methodwherein the one or more OPA chiplets are flip-chip integrated on top ofthe interposer, or placed next to the interposer. In certainembodiments, the method wherein a plurality of OPA chiplets are arrangedin a column. In certain embodiments, the method wherein the EAs from allOPA chiplets form an overall optical phase array aperture. In certainembodiments, the method wherein the optical distribution networkcomprises one or more selected from the group of waveguides, couplers,and passive devices to split an optical input from a laser source. Incertain embodiments, the method wherein further comprising the step of:connecting the interposer's input/output ports to the input/output portson the one or more OPA chiplets via optical couplings. In certainembodiments, the method wherein the coupling is between one or moreoutput waveguides on the interposer and one or more input waveguides onthe OPA chiplets. In certain embodiments, the method wherein thecoupling is structured as horizontal through edge-to-edge coupling. Incertain embodiments, the method wherein the coupling is structured asvertical by mode conversion between a plurality of tapered waveguides.In certain embodiments, the method wherein further comprising the stepof: fabricating an emission window. In certain embodiments, the emissionwindow is opened within the interposer as a through-substrate opening inthe region aligned with the EA on the one or more OPA chiplets. Incertain embodiments, the emission window is a backside opening patternedinto each OPA chiplet, wherein the opening can be patterned usingetching or other fabrication techniques. In certain embodiments, themethod further comprises the step of: fabricating a reflector on the OPAchiplet or on the interposer. In certain embodiments, the OPA chiplet isbuilt based on at least one of the following photonics technologies:silicon photonics (SiPh), silicon nitride photonics (SiN), hybridsilicon photonics (SiPh with SiN), lithium niobate photonics (LN), orIII-V photonics. In certain embodiments, the photonic waveguide layercomprises at least one of silicon, silicon nitride, lithium niobate, orIII-V materials.

Another aspect of the application is a method of improving emissionefficiency of a front or back emitting OPA chiplet, comprising the stepsof: positioning an emission window relative to an emission array,wherein the emission array is on an OPA chiplet, wherein front or backemitting light passes through the emission window from the emissionarray; positioning a reflector in relation to the emission array suchthat light propagated to the OPA chiplet substrate is reflected back tocombine with the light emitted to free space.

In certain embodiments, the method wherein further comprising the stepof: fabricating the device herein, wherein the device comprises thereflector positioned on the top surface of the OPA chiplet now facingdownward as shown in figures herein. In certain embodiments, the methodwherein further comprising the step of: fabricating the device herein,wherein the device comprises the reflector positioned on the interposer.

Another aspect of the application is a method of three-dimensionvertical coupling to improve optical power in OPAs, comprising the stepsof: positioning one or more emitters on an OPA chiplet on top of one ormore photonic waveguides on the interposer to form a bus waveguide in avertical coupling region of the device of above so that there is onewaveguide on the interposer feeding multiple emitters, wherein light iscoupled from the bus waveguide to the emitters in sequence or in otherfashions, including coupling to emitters in parallel.

In certain embodiments, the method wherein the coupling region is theactive device region for the phase shifter(s), wherein the phaseshifter(s) may be a thermo-optic phase shifter(s). In certainembodiments, the method wherein further comprising the step of:positioning heaters near one or more waveguides for the phase shiftersin the vertical coupling region, wherein the heaters are located on theinterposer or on the OPA chiplet.

Another aspect of the application is a system of complementarymetal-oxide-semiconductor (CMOS) electronics integrated with athree-dimensional integrated OPA device, comprising: the device herein;high-speed transceivers; signal processing; computer memory; and controlcircuitry.

Another aspect of the application is a method of manufacturing atwo-dimensional sparse optical phase array by layout-constrained arrayfactor optimization, comprising the steps of: determining the physicaldesign constraints for a baseline array comprising emitters in a uniformgeometric arrangement, wherein the physical design constraints comprisewaveguide routing requirements of a two-dimensional optical phase arrayaperture, and wherein array factors considered include beamwidth, spacedgrating lobes, steering range and sidelobes; allocating waveguiderouting space within the physical design constraints by reducing fillfactor among interior parts of the aperture, wherein the fill factor isthe ratio between an emitter footprint and emitter pitch in the opticalphase array; designing a thinned array of emitters in an arrangementdetermined by the allocation of waveguide routing space; designing asparse array by re-designing the thinned array based on a far-fieldpattern analysis of the array factors; mapping the emitters to anon-uniform grid geometry within the physical design constraints, orwherein the geometry of grids is uniform or non-uniform grids withbalanced patterns including square, circle or diamond.

In certain embodiments, the method wherein the non-uniform grid geometryis an asymmetric diagonal grid. In certain embodiments, the methodwherein the geometry of grids is uniform or non-uniform grids withbalanced patterns including square, circle, diamond or other geometries.

Another aspect of the application is a two-dimensional sparse opticalphase array comprising: a plurality of emitters; and a plurality ofwaveguide routers; and wherein each of the plurality of emitters isconnect to at least one of the plurality of waveguide routers andwherein the emitters are positioned to account for the physicalconstraints of the emitters and the waveguides.

In certain embodiments, the two-dimensional sparse optical phase arraymay have the emitters are positioned in a non-uniform grid geometry. Incertain embodiments, the two-dimensional sparse optical phase array mayhave the emitters positioned in a balanced pattern. In certainembodiments, the two-dimensional sparse optical phase array may have thebalanced pattern comprise one of a diagonal line, square, circle ordiamond.

Another aspect of the application is a method of use of the deviceherein for multiple wavelength OPA operation, wherein multiplewavelengths can share the OPA and correspondingly multiple beams betransmitted/received at different angular directions.

In certain embodiments, the method wherein an OPA-based LIDAR generatesmultiple beams in different angular directions without using multipleemitters pointing at different angular directions.

Another aspect of the application is a 3-D integrated OPA device,comprising: an interposer, wherein the silicon substrate can be used tofabricate CMOS electronics, and wherein there are one or more photonicwaveguide layers on the top; wherein an optical power distributionnetwork is located on the photonic waveguide layer(s); wherein one ormore phase shifters are connected to the optical power distributionnetwork; one or more OPA chiplets, which are 3-D integrated on theinterposer, wherein the interposer's input/output ports are coupled tothe OPA chiplets, and wherein the one or more OPA chiplets compriseemitter arrays (EA) and phase shifters; and further wherein theinterposer is integrated with the one or more OPA chiplets; and whereinthe OPA chiplet can operate in either transmit, receive, orsimplex/duplex mode, wherein simplex mode means that the OPA chiplet cantransmit or receive at different times, and duplex mode means that theOPA chiplet transmits and receives at the same time.

In certain embodiments, the device wherein the one or more OPA chipletsare integrated on top of at least one photonic waveguide layer. Incertain embodiments, the device wherein at least one photonic waveguidelayer is integrated on top of the one or more OPA chiplets.

Another aspect of the application is a monolithically integrated opticalphase array (OPA) device, comprising: an OPA chip; one or more EAs andphase shifters, wherein the one or more EAs and phase shifters arelocated on the OPA chip; CMOS electronics, wherein the CMOS electronicsmay be integrated on the OPA chip; two or more photonic waveguidelayers, wherein the photonic waveguide layers are integrated on the OPAchip; and an optical power distribution network, wherein the opticalpower distribution network is located on one or more of the photonicwaveguide layers and is connected to the phase shifters and EAs on theOPA chip.

One of ordinary skill will understand that the differing embodimentsdisclosed in this application can all be used either independently or incombination with each other and there is no limitation implied on suchcombinations by the order or manner in which embodiments are disclosed.

BRIEF DESCRIPTION OF THE DRAWINGS

While the present disclosure will now be described in detail, and it isdone so in connection with the illustrative embodiments, it is notlimited by the particular embodiments illustrated in the figures and theappended numbered paragraphs.

FIG. 1 illustrates an example of an optical phased array according to anembodiment of the present application.

FIG. 2 illustrates an example of an optical phased array with anemission window opened on the SiN interposer according to an embodimentof the present application.

FIG. 3 illustrates an example of an optical phased array with anemission window opened on the SiN interposer according to an embodimentof the present application.

FIG. 4 illustrates an example of an optical phased array according to anembodiment of the present application.

FIG. 5 illustrates an example of an optical phased array with anemission window according to an embodiment of the present application.

FIG. 6 is a flowchart illustrating steps of layout-constrained arrayfactor optimization process according to an embodiment of the presentapplication.

FIG. 7 is a baseline array according to an embodiment of the presentapplication.

FIG. 8 is a thinned array according to an embodiment of the presentapplication.

FIG. 9 is a sparse array according to an embodiment of the presentapplication.

FIGS. 10(a)-(c) are total patterns for the baseline, thinned and sparsearrays according to an embodiment of the present application.

FIG. 11 illustrates a heater geometry in an OPA according to anembodiment of the present application.

DETAILED DESCRIPTION OF THE INVENTION

Reference will be made in detail to certain aspects and exemplaryembodiments of the application, illustrating examples in theaccompanying structures and figures. The aspects of the application willbe described in conjunction with the exemplary embodiments, includingmethods, materials and examples, such description is non-limiting andthe scope of the application is intended to encompass all equivalents,alternatives, and modifications, either generally known, or incorporatedhere. Unless otherwise defined, all technical and scientific terms usedherein have the same meaning as commonly understood by one of ordinaryskill in the art to which this application belongs. One of skill in theart will recognize many techniques and materials similar or equivalentto those described here, which could be used in the practice of theaspects and embodiments of the present application. The describedaspects and embodiments of the application are not limited to themethods and materials described.

As used in this specification and the appended claims, the singularforms “a,” “an” and “the” include plural referents unless the contentclearly dictates otherwise.

Ranges may be expressed herein as from “about” one particular value,and/or to “about” another particular value. When such a range isexpressed, another embodiment includes from the one particular valueand/or to the other particular value. Similarly, when values areexpressed as approximations, by use of the antecedent “about,” it willbe understood that the particular value forms another embodiment. Itwill be further understood that the endpoints of each of the ranges aresignificant both in relation to the other endpoint, and independently ofthe other endpoint. It is also understood that there are a number ofvalues disclosed herein, and that each value is also herein disclosed as“about” that particular value in addition to the value itself. Forexample, if the value “10” is disclosed, then “about 10” is alsodisclosed. It is also understood that when a value is disclosed that“less than or equal to “the value,” greater than or equal to the value”and possible ranges between values are also disclosed, as appropriatelyunderstood by the skilled artisan. For example, if the value “10” isdisclosed the “less than or equal to 10” as well as “greater than orequal to 10” is also disclosed.

The present application is further illustrated by the following examplesthat should not be construed as limiting. The contents of allreferences, patents, and published patent applications cited throughoutthis application, as well as the Figures and Tables, are incorporatedherein by reference.

EXAMPLES

The present application provides various embodiments as described below.One embodiment of the present application provides a three-dimensional(3-D) integrated optical phase array (OPA) design and supportingtechnologies. As shown in FIG. 1, the OPA device 100 is constructed as a3-D integrated system with a photonic waveguide layer. This may includea SiN interposer 102 and M silicon-on-insulator (SOI) OPA chiplets 104,such as a silicon photonic (SiPh) chips, on top. While FIG. 1 shows fourOPA chiplets 104, which may also be referred to as OPAs, may be on theSiN interposer 102, it is understood that more or fewer four OPAchiplets 104 may also be used. The embodiment allows a number of OPAchiplets 104 to be mounted on SiN interposer 102 as part of an overallsystem-on-chip (SoC). This 3-D structure of SiPh-on-SiN may also beimplemented as SiN-on-SiPh where the technology allows SiN layers on topof the SiPh chip. Other embodiments and configurations may also be used.

Each of the OPA chiplets 104 may have optical input/output ports thatare coupled to optical input/output ports an interposer 102. On theother side of the interposer 102, there may be one or more opticalinput/output ports to couple to (a) one or more fibers or lasers whenthe OPA chiplets 104 operate in the transmit mode, or (b) one or morefibers or photodetectors when the OPA chiplets 104 operate in thereceive mode. Further, there may be phase shifter on the interposer 102.In addition, the OPA chiplets may be 3-D integrated on an interposerwith at least one photonic waveguide layer. The photonic waveguide layermay be separated from the silicon substrate, or another photonicwaveguide layer, by cladding materials.

The OPA chiplets 104 may be is built based on at least one of thefollowing photonics technologies: silicon photonics (SiPh), siliconnitride photonics (SiN), hybrid silicon photonics (SiPh with SiN),lithium niobate photonics (LN), or III-V photonics The photonicwaveguide layer comprises at least one of silicon, silicon nitride,lithium niobate, or III-V materials. Other materials may also be used.Further, an integrated waveguide may consists of two materials: a corematerial, and another cladding material surrounding it. Both may bedielectric materials. In the SiPh case, the core material may besilicon, and the cladding is SiO₂. In the SiN case, the core may besilicon nitride, and the cladding is still SiO₂. Other materials mayalso be used.

Each OPA chiplet 104 may consist of an array of emitters (EA) 106 andsupporting phase shifters 108. While FIG. 1 illustrates one EA 106 oneach OPA chiplet 104 and four supporting phase shifters 108 for each EA106, it is understood that more or fewer EA's 106 and more or fewersupporting phase shifters 108 may also be used. There are N inputwaveguides on the OPA chiplet to N sub-arrays of emitters 106. The OPAchiplets 104 can be flip-chip integrated to the SiN interposer 102, asshown here. Alternatively, an OPA chiplet 104 may be placed face up, maysit next to the interposer, or sit in a cavity in the interposer. Thenedge coupling is used to connect them. Other 3-D integration techniquesmay also be used. FIG. 1 illustrates an example of the layout of the 3-Dintegrated chip stack, in which the OPA chiplets 104 are positioned in acolumn. Other layout arrangements may be implemented as well.

By using the EAs 106 from many small OPA chiplets 104 to form theoverall OPA aperture 100, the cost of OPA chiplet fabrication may bereduced. Additional cost saving may be achieved for the overall OPAsystem 100 as the chiplet design may improve the yield of the packaged3-D chip by allowing the discarding of bad SiPh dies before 3-Dintegration. That is, each OPA chiplet 104 may be tested prior tointegration with SiN interposer 102.

On the SiN interposer 102, there may be an optical power distributionnetwork 110 made of waveguides, couplers (such as multi-modeinterferometers or MMIs), and other passive devices to split the opticalinput from the laser source (not shown) to M×N outputs. In embodimentsof the present application, portions of the optical power distributionnetwork 110 may be off chip. There may also be phase shifters 108 on theSiN interposer 100 to set the bias across the outputs. These phaseshifters 108 may be used to compensate for the phase variations on theSiN interposer chip 102 and across OPA chiplets 104. Other circuitry mayalso be included on and in connection with OPA 100.

By locating the optical power distribution network 110 on the SiNinterposer 102, the power handling bottleneck of silicon waveguides maybe reduced or eliminated. This may result in an increase in totaloptical power that may be output by the OPA 100. The 3-D chip stackstructure may further allow complex waveguide routing underneath the OPAchiplets 104, resulting in finer emitter pitch, e.g., shorter distancebetween center-points of the emitters. Multiple SiN interposer layers102 also may be implemented to further increase the routing density. Thecoupling region may consist of the waveguide couplers on both interposerand OPA chiplet, as well as any dielectric in between. FIGS. 1-5illustrate the OPA operates in the transmit mode, i.e., “Laser in” and“Light out”. When the OPA operates in the receive mode, the signals willbe opposite, such that, for example, in FIG. 2, the “Laser In” label atthe output waveguides 118 would be replaced by a “Light toPhotodetector” label, and the “Light Out” label from the EA 106 would bereplaced by a “Light Received.” In an embodiment of application, theoptical distribution network comprises one or more of waveguides,couplers, and passive devices such that when in receive mode, theyfunction to split an optical input from laser source in the transmitmode, or to combine the light received from all OPA chiplets in thereceive mode.

Optical coupling between the output waveguides 118 on the SiN interposer102 and the input waveguides 120 on the OPA chiplets 104 may beperformed in various manners. One such manner may be horizontal throughend-to-end coupling, which is illustrated in FIGS. 2 and 3. In anembodiment of the application, a vertical coupling region 112 betweenthe two chips may be made of a low index dielectric material, such asoptical polymers, which also may serve as the underfill for theflip-chip integrating process. Other materials may also be used. In anembodiment of the application, there may be both silicon waveguide andSiN waveguide layers in the same chip. In such an embodiment, there maybe two or more photonic waveguide layers: one for EA and phase shifters,and another (or more) for the optical power distribution network. Whilesuch an embodiment may be implemented using a hybrid SiPh+SiNtechnology, other technologies may also be used.

Another manner of optical coupling may be vertical by mode conversionbetween two tapered waveguides. Vertical coupling by mode conversion mayresult in high coupling efficiency, which in some instances may be closeto 100%. Vertical coupling may also relax the alignment accuracyrequirement between the two tapered waveguides. Other manners ofvertical coupling may also be used.

The present application further provides different designs for theemission window, through which light is transmitted outward from the EA106 to free space, or received from free space by the EA 104 when theOPA operates as a receiver. FIG. 2 illustrates one embodiment of thepresent application, where the emission window 114 is opened on the SiNinterposer 102 as a through-substrate via (TSV) hole in the area facingthe EA 106 on the OPA chiplets 104. As noted, a SiN waveguide 118 isprovided on the photonic waveguide layer of SiN interposer 102, while aSiPh waveguide 120 is provided on the photonic waveguide layer of theOPA chiplets 104. Light leaves the EA 106 and travels through theemission window 114 of the SiN interposer 102.

FIG. 3 illustrates another embodiment of the present application of adesign for the emission window 114, where the EA 106 operates in theback emission mode. A backside opening is etched into the siliconsubstrate of the OPA chiplets 104 to open the emission window for theEA. The backside etching process may be stopped by a buried oxide (BOX)layer, and may be similar to that for bulk silicon MEMS device. Theemission window 114 therefore may be well controlled with cleanboundaries defined by silicon crystal planes. To facilitate the etchingprocess, the OPA chiplets 104 may be thinned down first. Other mannersof fabricating the OPA chiplets 104 may also be used.

The emission efficiency of the back-emission EA 104 may also be improvedby having a reflector 116 fabricated on a surface of the OPA chiplets104. The OPA chiplets 104 may then be positioned such that the reflector116 is located between the SiPh chip 104 and the SiN interposer 102. Thereflector 116 may be of a metal, such as aluminum or silver. Othermaterials, including non-metal materials, may also be used for reflector116.

Alternatively, the reflector 116 may be placed on the surface of the SiNinterposer 102. By way of example, reflector 116 may be a mirror made ofa metal layer, a grating, or other types of reflectors. The reflector116 reflects the emitting light from the emitter back to the upwarddirection to be combined with the original back emitting light. Whenthese two lights interfere constructively with the proper reflectordistance, the emission efficiency may be improved compared to the topemitting only case. Emission efficiency may increase from less than 70%to over 95%. In addition, this back-emitting OPA design may be alsoapplied to the OPA chiplet 104 alone in conventional technologies,independent of 3-D integration. Other configurations may also be used.

FIGS. 4 and 5 illustrate an example of an optical phased array accordingto an embodiment of the present application. Like components areidentified with the same reference numbers as the embodiment of FIGS.1-3. FIGS. 4 and 5 illustrate a 3-D integration scheme based on edgecoupling between the interposer 102 and OPA chiplets 104. Thus, theembodiment of the present application may be slimmer, as the interposerand OPA chiplets 104 may be in the same plane.

According to the present application, additional integration schemes maypotentially be more compact in which light is directly coupled from theSiN waveguide on the SiN interposer 102 vertically to multiple emittersin the EA 106 of the OPA chiplet 104. For example, the emitters in a rowon the OPA chiplet 104 may be positioned on top of the SiN waveguide 118in the coupling region, thereby allowing light to be coupled from thebus waveguide to these emitters in sequence. Since the optical modeexpands gradually as light propagates in the bus waveguide, couplingcoefficients may increase gradually between the bus waveguide and theemitters. This may effectively compensate for the decreasing opticalpower in the bus waveguide, and thus equalize the optical power coupledto each emitter. This may avoid the requirement of additional opticalcouplers between the bus waveguide and emitters. By utilizing theintrinsic characteristics of 3-D vertical coupling, the need forcouplers to have different coupling coefficients to equalize the coupledpower to each emitter may be reduced while also accurately controllingthe nanometer gap size in fabrication.

The vertical coupling region may also be simultaneously used forthermo-optic phase shifters to save chip area. Some optical polymers mayexhibit large thermo-optic coefficients, e.g., dn/dT=−1.3×10⁻⁴ K⁻¹ forpolymethyl methacrylate (PMMA), which is comparable in absolute value tothat of silicon at 1550 nm. Heaters, such as resistive heaters, may beimplemented on the SiN interposer 102 or SiPh chip 104 in the couplingregion near the waveguides 118, 120 for these phase shifters 108. Othertypes of heaters may also be used.

Further, the polymer thermo-optic phase shifter design may be combinedwith the aforementioned scheme of direct vertical coupling co-emitters.In this embodiment, one or more heaters may be used to apply a phaseshift to the entire coupling region and thus tune the phases of all theemitters in a linearly scaled fashion. Such a phase shifter design maybe compact in chip area, energy efficient, and accurate in phasecontrol.

CMOS electronics may be implemented on the SiN interposer 102 or on aseparate chip also 3-D integrated on the SiN interposer 102. The 3-Dchip stack may then become a complete electronic-photonic integratedsystem. High-speed transceivers, signal processing, memory, and controlcircuitry may be integrated with photonics to improve the performance,reduce energy, and enable new functionalities for the OPA system 100.Such a solid-state solution with no moving parts may exhibit improvedperformance in terms of cost, size, weight and reliability.

3-D OPAs according to embodiments of the present application may be usedin LIDAR applications, due to their advantages in cost, size, weight,reliability, and power consumption as compared to conventionalsolutions. Large-scale OPAs can leverage high integration densities ofelectronic-photonic integrated circuit (EPIC) technology to generatefiner beamwidth, and better beamsteering control.

To meet the stringent performance requirements in real worldapplications, embodiments of the present application may provide 3-DOPAs with higher output optical power, a larger number of emitters withsmaller pitch size, and a larger aperture. The present application alsoworks with silicon photonics technologies, which are a common technologychoice for integrated OPA development because of the low fabricationcost and electronic-photonic integration capabilities enabled by maturesilicon based semiconductor infrastructures driven by CMOS electronicsindustry. Silicon may offer low-loss optical waveguide devices for twomain components of an OPA: grating emitters and phase shifters.

Embodiments of the present application may reduce or eliminate some ofthe issues with silicon in high-power, large-scale OPA implementations.The issues that may be improved or eliminated include silicon waveguidesrelatively low optical power handling capability due to the large lossof high optical power caused by two-photon absorption. Further, siliconphotonic devices are often built on the top silicon layer of asilicon-on-insulator (SOT) chip. The present application may avoidsingle device layers that prohibit complex waveguide routing and mayseverely limit how the array of emitters are connected to the phaseshifters, especially for 2-D OPAs. The present application may alsoimprove the emission efficiency of the grating emitter.

Embodiments of the present application addresses these and other issuesbased on 3-D heterogeneous integration of both SOI and silicon nitride(SiN) photonics. By 3-D integration of both SOT and SiN photonics, thepresent application takes advantage of both technologies and achievesignificant performance gains in high-power, large-scale OPAs.

According to embodiments of the present application, a sparse OPA designbased on layout-constrained array factor optimization (LCAFO) may beused in an OPA for various applications. LCAFO is a scalable designmethodology to optimize 2-D OPAs. FIG. 6 illustrates how a LCAFO may becarried out. FIG. 7 illustrates a starting design of a 2-D OPA. The OPA300 includes a number of emitters in starting positions 302. In thisexample, the original emitter starting positions 302 are located inrectangular shape of rows and columns. Any number of emitters instarting positions 302 may be used.

At step 202, the method may determine physical design constraints. Atstep 204, it may allocate waveguide routing space. At step 206, it maydesign a thinned array of emitters. At step 208, it may design a sparsearray of emitters. At step 210, the emitters are mapped. The method ofFIG. 4 will now be described in more details.

At step 202, the method may determine physical design constraints.Design constraints in the array implementation may include the waveguiderouting requirements of a 2-D OPA aperture. This may include determininghow much space is necessary for the waveguide routing for each emitteras well as the location and arrangement of that waveguide routing. Otherconstraints may also be determined and used in the design.

At step 204, the method may allocate waveguide routing space. This mayinclude determining what space is necessary to connect waveguide to theemitters. It may also involve determining the location and arrangementof that waveguide routers. To satisfy the layout constraints, waveguiderouting space may be allocated by reducing the fill factor among theinterior parts of the aperture. In one example, the fill factor may bethe ratio between an emitter footprint and emitter pitch in an opticalarray. This may result in a thinned array of emitters. An embodiment ofthe present application as shown in FIG. 8 illustrates the originalrectangular pattern of emitters being divided into two halves of thinnedemitter positions 304. It is understood that the entire rectangle ofemitters can be manipulated. Alternatively the rectangular pattern ofemitters may be dived up into three or more sections for manipulation.

At step 206, the method may design a thinned array of emitters. Thethinned array of emitters has fewer emitters than those in the originalemitter configuration. Designing a thinned array may involve determinewhich emitters are kept and which emitters are eliminated, as thepositions of the kept emitters. As shown in FIG. 8, the emitters are nowlocated in the thinned positions 304. In this example, the thinnedemitter positions are in rows. For reference, both the originalpositions 302 and the thinned positions 304 are shown to illustratewhich emitters were removed in the example of the thinned design fromstep 206.

At step 208, the method may design a sparse array of emitters. In anexample, the thinned array may re-designed and the thinned positions 304may be mapped to a non-rectangular and potentially non-uniform gridgeometry with the layout constraints based on far-field pattern analysisof the array factor. Thus, new sparse emitter positions 306 aredetermined based on a configuration that accounts for the physicaldesign constraints, including the waveguide routing. For example, anasymmetric diagonal grid may be used. Other configurations may also beused.

At step 210, the emitters are mapped to the sparse positions 306. By wayof example, FIG. 9 illustrates the emitters in the sparse positions 306which are in two diagonal configurations that when put together faun abent configuration. However, the sparse emitter positions 306 may formother configurations, such as square, circle, diamond, triangle, orother arrangements, and either alone or together. Again, for reference,both the original positions 302 and the sparse positions 306 are shownto illustrate which emitters were removed in the sparse design from step210.

FIGS. 7-9 further illustrate examples of the light intensities for eachof the dense (or baseline), thinned and sparse emitter configurations.As illustrated, the intensity of the light from the sparse emitterconfiguration in FIG. 9 is substantially similar to that in the denseconfiguration in FIG. 7. Thus, the sparse configuration may be used inmany of the same applications that a dense or baseline configurationcould be used in.

Use of a LCAFO and the resulting sparse OPA design may have advantages,as waveguide routing is taken into account and hence more feasible forlarge scale arrays. Further, the fill factor may be much higher than aconventional sparse array design in a rectangular grid. In addition, a2-D OPA designed using LCAFO may maintain some or all of the beamformingand beamsteering performance of a dense rectangular array. A designusing LCAFP may be scalable to a larger size as well as compatible withadvanced array architectures such as subarray designs. The solutionspace in LCAFO also may be significantly reduced, and the array may besystematically optimized to produce a scalable OPA. Further, the sparsearray positions from the LCAFO method may be in well-defined locations.LCAFO methodology may also be compatible with subarray designs bymaintaining the proximity of emitters in the same subarray. In addition,LCAFO may maintain the balanced subarray architecture to achieve highertotal output optical power. Further, the LCAFO method may enable novelOPA designs with new functionalities, e.g., multiple beam generation bya single OPA. One of ordinary skill would understand that additionalperformance goals may be added into LCAFO designs.

As noted previously, the LCAFO method is illustrated conceptually in theexample illustrated in FIGS. 7-9. The designs in the baseline (FIG. 7),thinned (FIG. 8), and sparse (FIG. 9) arrays show a typical designevolution using this method. The baseline array may have emitters on adense rectangular grid, and exhibit ideal array factor properties, suchas narrow beamwidth, far spaced grating lobes and hence large steeringrange, and weak side lobes. As noted, the high density of emitters mayrestrict waveguide routing area. A layout constraint may be imposed onthe baseline array to allow waveguide routing. In this example, thewaveguides may be routed from both sides of the array to the emitters,which essentially splits the array into two halves. In this example theconstraint is applied by removing intermediate rows of the baselinearray and thereby producing a thinned array in FIG. 8.

Each emitter in the thinned array illustrated in FIG. 8 may be directlyfed with an optical waveguide. After thinning, however, the fill factorof the thinned array may be significantly reduced in the verticaldimension. This may introduce significant grating lobes in the arrayfactor pattern or the thinned array in the θ direction. To recover theperformance of the baseline array, the emitters in the thinned array maybe re-mapped to a diagonal geometry grid as shown in FIG. 9. The arrayfactor pattern shows a more even spread of grating lobe energy. Thus,the resulting sparse array design may exhibit a larger effectivevertical till factor.

The total patterns of the baseline, thinned, and sparse arrays accordingto the present application are illustrated in FIGS. 10(a)-(c)respectively. Specifically, the intensity, phase and offset is show foreach. These patterns are the product of the array factor (AF) and thefar-field element pattern (EP) of a single emitter. As shown in thepatterns in 310 in the ϕ-cuts 310, the total patterns may be similarsince horizontal emitter density is maintained in all three arrays.Comparing the θ-cuts 312 of the total pattern, the large grating lobesin TP_(Thinned) may be significantly reduced in TP_(sparse). The sparsearray may achieve a good approximation of the orthogonal patternproperties of the baseline array with 5x reduction in emitters.

A non-uniform sparse array of emitters may be able to relax the designtradeoffs for large-scale 2-D OPAs. This will benefit the use of OPAs inLIDAR applications, as well as leverage high integration densities ofelectronic-photonic integrated circuit technologies to generate finerbeamwidth and better beamsteering control. Sparse array emitters mayincrease the ability to scale up 2-D OPAs to meet the performancerequirements for real world application. New array architectures,aperture optimization methodologies, and novel array geometries may benecessary to address tradeoffs for OPA's beamwidth and beamsteeringperformance.

In an embodiment of the present application, sparse array designs may beused in radio frequency (RF) phased array systems to alleviate thecomplexity and cost of large uniform arrays. In the RF domain, the goalof sparse array designs may be to reduce the fill factor of a uniformarray by selectively removing emitters. In an optimized sparse array,the beamwidth of the uniform may be preserved with fewer emitters. Thisthinning procedure may be extended to the optical domain to create asparse OPA. Since the aperture of a sparse OPA has fewer emitters thanan equivalent uniform array, the available area for waveguide routing isincreased. Further, crosstalk may be easier to manage in a sparse OPA.

The beam formed pattern of a sparse array aperture may be highlysensitive to the number and relative location of the emitters. There isno closed-form solution to guide the optimization of a sparse aperture.In an embodiment of the present application, a genetic algorithm of thepresent application may numerically emulate the evolutionary behaviorsof DNA: mutation, crossover, and natural selection. When applied tosparse array optimization, the algorithm of the present application maytreat each emitter as a switch and enforce constraints on beamwidth,sidelobe levels, emitter pitch, routing clearance, and emitter location.As noted previously, a sparse OPA design based on genetic algorithm maystart from a reference array with a uniform rectangular grid within afixed aperture. The optimized sparse array produced by the geneticalgorithm may follow this uniform rectangular grid defined by thereference array. The genetic algorithm may optimize array performancewithout much consideration for the feasibility of implementation. Therectangular grid geometry may set an upper limit on the fill factor(density) of the optimized array aperture. Since beamforming andbeamsteering performance of the array may be affected by the aperturefill factor, the rectangular array geometry may impose a limitation onarray performance. A non-rectangular sparse array design may lead toimproved OPA performance.

In another embodiment of the present application, during all or part ofthe beamsteering scan range, the coefficients of the OPA phase shiftersmay be changed in a consistent direction. For thermo-optic phaseshifters, this means that the temperatures of the phase shifters may beeither increased or decreased in the same direction. In one embodimentof an OPA beamsteering operation, the phase shifter coefficients aretypically changed step by step, and at each step, the detection isperformed after the transition so that the coefficients stabilize.

To speed up the beamsteering process, the transition of the phaseshifter coefficient changes may be utilized for beamsteering. Forthermo-optic phase shifters, their temperatures are increased (ordecreased) linearly with time by controlling heater currents withinheaters. During this transition when the temperatures ramp up (or down),the OPA's beam continuously scans across an angular range. An embodimentof the present application may include either slowing down thetransition or adopting a fast detection mechanism in the receiver orboth. In this embodiment, multiple detection samples may be taken duringthis transition, each at a separate angular position. The settling timefor each detection may be reduced or essentially cut down to zero insuch a continuous beamsteering operation of the OPA. Further, thetemperature rise (or fall) may be predicted over time. This may allowthe coefficient to be predicted and applied, thus reducing oreliminating the time needed for each step change to occur.

To generate the desired temperature ramp duration and linearity ofthermo-optic phase shifters, heater currents are controlled inpre-defined waveforms, and monitored during the transition to correctany error by a feedback loop. The temperatures at each detection samplemay be measured using temperature sensors embedded in the OPA chip, orderived from the heat currents. Other manners of measuring thetemperature may also be used.

The OPA's phase shifter arrays may be optimized in the design bymaximizing the spatial and time correlation of the phase shiftercoefficients during the transition. For example, a single heater cangenerate a temperature gradient in a number of phase shifters, and thephysical distances between them may determine the transition time forheat to transfer among them and hence the temperature ramp.Alternatively, a plurality of heaters may be used.

Optical variable phase shifters may be realized by exploiting thethermo-optic and electro-optic effect of silicon. In an embodiment ofthe present application, electro-optic may be preferred in peripheralinterface controllers for high speed (GHZ) communications due to theirfast response time (in ns), at the expense of large circuit footprint.However, in phased array applications, phase shifter footprint may takepriority over modulation speed, especially in 2-D arrays. Heater devicesmay be made more compact (sub-λ) than their electrical counterpart. In2-D phased arrays, slow (in μis) modulation by the thermo-optic effectmay be tolerable with these compact heater devices as they enable themonolithic integration of both electronic and photonic devices on asingle chip.

An optical phase shifter may control the phase of a propagating opticalmode. The thermo-optic effect may be a simple and cost-effectivetechnique to manipulate optical phase. A primary aspect in thermal phaseshifter design may be thermal efficiency. Thermal efficiency may definethe ability of the heater to convert electrical power to optical phaseshift.

By introducing a heater into the optical path of a grating coupler, thepropagating optical mode feeding the grating coupler can be delayed.This delay may not be particularly meaningful for a single gratingcoupler. However, if the grating coupler is part of an array,introducing a relative phase delay between adjacent grating couplersallows for direct control of the interference properties of the emittedlight. By treating each grating coupler in the array as a radiatingaperture, the far-field representation of the array may be adistribution of point sources, each emitting an electromagnetic wave.These electromagnetic waves interfere constructively and destructively.By thermo-optically inducing a constant phase delay between adjacentgrating couplers, the constructive interference peak may be localized ina specific direction. Thus, the optical beam from the array of gratingcouplers may be steered in a controlled manner.

An array of grating couplers may require one or more heaters. Aplurality of heaters may be arranged as an array of heaters. Whereasoptical interference between adjacent grating couplers is desired andleveraged, thermal interference between adjacent heaters within an arrayof heaters may be undesirable. Large heater pitch may alleviate thermalcrosstalk but increases the circuit footprint. Thus, an increase heaterpitch may not be practical for hundreds to thousands of gratingcouplers. An alternative approach to limit thermal crosstalk in acompact footprint is to isolate adjacent heaters. For this technique tobe feasible on a large scale, the isolation mechanism should notincrease fabrication complexity. Etched air trenches between adjacentheaters may be a viable means of addressing the crosstalk challenge.However, the density of the heater array may set the upper limit ontrench size, and the minimum aspect ratio of the fabrication process mayset a lower limit on trench size. Therefore, the impact of isolating airtrenches on heater thermal efficiency within practical fabricationmargins must be considered.

FIG. 11 illustrates a heater geometry in an OPA according to anembodiment of the present application. As illustrated, a heater designmay focus on the metal-over-waveguide heater geometry flanked by airtrenches to enhance heat confinement. A cross-sectional view of thephase shifter 400 is shown in FIG. 11 with a standard silicon photonictechnology based on a silicon-on-insulator (SOI) substrate 402 with asilicon top layer 404 and a buried oxide (BOX) layer 406. In anembodiment of the present application, the silicon layer 404 may be220-nm and BOX layer 406 may be 3-μm thick. The phase shifter consistsof a strip waveguide 408 and a titanium (Ti) resistive heater above itthat is 110 nm thick. In an embodiment of the present application, thesilicon layer 404 is formed into a strip waveguide 408 which may havedimensions of 220-nm×450-nm. SiO₂ cladding layers 412, and air trenches414 may be etched on both sides of the strip waveguide 408. Whilevarious dimensions have been described for various elements, it isunderstood that other dimensions may be used. Various design parametersfor the heater 410 may be consider. These parameters may include avertical heater-to-waveguide gap (HWG), a horizontal trench-to-heatergap (THG), a trench width (TW), a heater width (HW), and a heater length(HL). In an embodiment of the present application, HWG may be a processparameter determined by the SiO₂ layer thickness below the Ti heater410. The design parameters may be physical design parameters determinedby the layout but are also bounded by the fabrication limitations(design rules).

In an embodiment of the present application, HWG and HW may be thedominant factors, as the closer the heater 410 is placed to thewaveguide 408, the higher the thermal efficiency. In addition, the moreconcentrated the heat is generated, the better. The HWG may be lowerbounded by the heater induced optical loss, while the HW may be loweredbounded by lithography and etching processes. Because of the linearrelationships between heater power per unit length and temperaturechange (hence phase change), the heater length may barely affect thethermal efficiency. That is, the longer the heater length, the lowerheater power per unit length, and the smaller the temperature change.Thus, the overall phase change may remain the same. The heater lengthmay affect the heater's electrical resistance and hence the requiredvoltage applied to the heater. In an embodiment of the presentapplication, the maximum operation temperature and maximum controlcircuit voltage may set the lower and upper bounds of the heater length.

The thermal efficiency may be improved with the addition of air trenches414. The generated heat may be confined within the thermal cavity andincrease the thermal resistance. That is, heat generated in heater 410may radiate to waveguide 408 and may not radiate as effectively throughair trenches 414. A 67% reduction in thermal efficiency may be achievedfor the same HWG, HW, and HL conditions when using an air trench 414.The performance may be further enhanced by optimizing thetrench-to-heater gap (THG) in FIG. 9. For example, for HW=1 μm, HWG=0.2μm, and HL=330 μm, an additional 50% reduction in thermal efficiency maybe achieved when THG is reduced from 1.5 μm to 0.5 μm. In an embodimentof the present application, when THG is reduced to 100-nm, a thermalefficiency of 2.8-mW/π may be achieved. While an embodiment of oneconfiguration is illustrated in FIG. 9, it is understood that otherconfigurations may be used.

The various embodiments of the present application may be used alone orin combination with one or more other embodiments. Thus, as an example,the algorithm for the 2-D sparse OPA may be used in connection with the3-D integrated optical phased array and the heater structure. Othercombinations may also be used.

While various embodiments have been described below, it should beunderstood that such disclosures have been presented by way of exampleonly and are not limiting. Thus, the breadth and scope of the subjectcompositions and methods should not be limited by any of theabove-described exemplary embodiments, but should be defined only inaccordance with the following claims and their equivalents.

The description herein is for the purpose of teaching the person ofordinary skill in the art how to practice the embodiments of the presentapplication, and it is not intended to detail all those obviousmodifications and variations of it which will become apparent to theskilled worker upon reading the description. It is intended, however,that all such obvious modifications and variations be included withinthe scope of the embodiments of the present application, which isdefined by the following claims. The claims are intended to cover thecomponents and steps in any sequence which is effective to meet theobjectives there intended, unless the context specifically indicates thecontrary.

1. A three-dimensional (3-D) integrated optical phase array (OPA) chipdevice, comprising: an interposer, the interposer comprising photonicwaveguide layers are on top of a silicon substrate and having at leastone optical input/output port; an optical power distribution network,wherein the optical power distribution network is located on thephotonic waveguide layers of the interposer; and one or more OPAchiplets, wherein each OPA chiplet comprise phase shifters and photonicwaveguides and having at least one optical input/output port; whereinthe at least one optical input/output ports of the OPA chiplets arecoupled to the at least one of the optical input/output ports of theinterposer; wherein the one or more OPA chiplets comprise emitter arrays(EA), and wherein the OPA chiplet can operate in either transmit,receive, simplex, or duplex mode, wherein simplex mode means that theOPA chiplet can transmit or receive at different times, and duplex modemeans that the OPA chiplet transmits and receives at the same time. 2.The device of claim 1, wherein OPA chiplets are 3-D integrated on aninterposer with at least one photonic waveguide layer, wherein thephotonic waveguide layer is separated from the silicon substrate, oranother photonic waveguide layer, by cladding materials.
 3. The deviceof claim 1, wherein at least one photonic waveguide layer is fabricatedon the silicon substrate and then patterned using lithography to becomepart of the interposer.
 4. The device of claim 1, wherein one or morewaveguides on the one or more OPA chiplets feeds one or more sub-arraysof emitters, wherein each waveguide may feed a single emitter or asubarray of emitters.
 5. The device of claim 1, wherein the one or moreOPA chiplets are 3-D integrated with the interposer by flip-chip bondingor multi-chip module.
 6. The device of claim 1, wherein the EAs from allOPA chiplets form an overall optical phase array aperture for thedevice.
 7. The device of claim 1, wherein the optical distributionnetwork comprises one or more selected from the group of waveguides,couplers, and passive devices to split an optical input from a lasersource when the device operates in the transmit mode, or to combine thelight received by all OPA chiplets when the device operates in thereceive mode.
 8. The device of claim 1, further comprising an emissionwindow.
 9. The device of claim 8, the emission window is an opening atthe backside of each OPA chiplet, wherein the opening can be patternedusing etching.
 10. The device of claim 9, further comprising areflector, wherein the reflector is a minor, or a grating, or other typeof reflector, wherein the reflector may be on the interposer or on theOPA chiplet.
 11. The device of claim 1, wherein the OPA chip device isconfigured for multi-wavelength operation.
 12. The device of claim 1,wherein the OPA chip device is configured for multi-beam operation. 13.The device of claim 1, further comprising an active device region forthe phase shifter(s), wherein the phase shifter(s) may be a thermo-opticphase shifter(s); and. wherein at least one heater is positioned nearone or more waveguides for the phase shifters, wherein the at least oneheater is located on the interposer or on the one or more OPA chiplets.14. The device of claim 13, further comprising at least one airtrenchpositioned between each heater, wherein the airtrench isolates eachheater from the other.
 15. A two-dimensional sparse optical phase arraycomprising: a plurality of emitters; and a plurality of waveguiderouters; and wherein each of the plurality of emitters is connect to atleast one of the plurality of waveguide routers and wherein the emittersare positioned to account for the physical constraints of the emittersand the waveguides.
 16. The two-dimensional sparse optical phase arrayof claim 15, wherein the emitters are positioned in a non-uniform gridgeometry.
 17. The two-dimensional sparse optical phase array of claim15, wherein the emitters are positioned in a balanced pattern.
 18. Thetwo-dimensional sparse optical phase array of claim 17, where thebalanced pattern comprises one of a diagonal line, square, circle ordiamond.
 19. A three-dimensional (3-D) integrated optical phase array(OPA) chip device, comprising: an interposer, wherein the siliconsubstrate can be used to fabricate CMOS electronics, and wherein thereare one or more photon waveguide layers; wherein an optical powerdistribution network is located on the photon waveguide layer(s);wherein one or more phase shifters are connected to the optical powerdistribution network; one or more OPA chiplet s, which are 3-Dintegrated on the interposer, wherein the one or more OPA chipletscomprise emitter arrays (EA) and phase shifters; and further wherein theinterposer is integrated with the one or more OPA chiplets; and whereinthe OPA chiplet can operate in either transmit, receive, orsimplex/duplex mode, wherein simplex mode means that the OPA chiplet cantransmit or receive at different times, and duplex mode means that theOPA chiplet transmits and receives at the same time.
 20. The device ofclaim 19, wherein the one or more OPA chiplets are integrated on top ofat least one photon waveguide layer.
 21. The device of claim 19, whereinat least one photonic waveguide layer is integrated on top of the one ormore OPA chiplets.